[all-commits] [llvm/llvm-project] 4bc6f6: [TargetLowering] SimplifyDemandedBits - fix SCALAR...
Simon Pilgrim via All-commits
all-commits at lists.llvm.org
Fri Feb 28 07:23:48 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 4bc6f63320289e280fd848d163ada995f5fe679b
https://github.com/llvm/llvm-project/commit/4bc6f63320289e280fd848d163ada995f5fe679b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2020-02-28 (Fri, 28 Feb 2020)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
M llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
M llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
M llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/X86/insertelement-ones.ll
M llvm/test/CodeGen/X86/load-partial.ll
M llvm/test/CodeGen/X86/pr30562.ll
M llvm/test/CodeGen/X86/sse3.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
Log Message:
-----------
[TargetLowering] SimplifyDemandedBits - fix SCALAR_TO_VECTOR knownbits bug
We can only report the knownbits for a SCALAR_TO_VECTOR node if we only demand the 0'th element - the upper elements are undefined and shouldn't be trusted.
This is causing a number of regressions that need addressing but we need to get the bugfix in first.
Commit: b6e80864b6da7937504dcf5698ea49801d1f7be2
https://github.com/llvm/llvm-project/commit/b6e80864b6da7937504dcf5698ea49801d1f7be2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2020-02-28 (Fri, 28 Feb 2020)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
Log Message:
-----------
Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFCI.
Compare: https://github.com/llvm/llvm-project/compare/2809abbd9898...b6e80864b6da
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