[all-commits] [llvm/llvm-project] 13db74: [AArch64] Peephole optimization: merge AND and TST...

[sjoerdmeijer via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 13db7490fa67e22605dec4ab824121230b0fd928
      https://github.com/llvm/llvm-project/commit/13db7490fa67e22605dec4ab824121230b0fd928
  Author: Sjoerd Meijer <sjoerd.meijer at arm.com>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/funnel-shift.ll
    A llvm/test/CodeGen/AArch64/peephole-and-tst.ll
    M llvm/test/CodeGen/AArch64/shift-by-signext.ll

  Log Message:
  -----------
  [AArch64] Peephole optimization: merge AND and TST instructions

In some cases Clang does not perform merging of instructions AND and TST (aka
ANDS xzr).

Example:

  tst x2, x1
  and x3, x2, x1

to:

  ands x3, x2, x1

This patch add such merging during instruction selection: when AND is replaced
with ANDS instruction in LowerSELECT_CC, all users of AND also should be
changed for using this ANDS instruction

Short discussion on mailing list:
http://llvm.1065342.n5.nabble.com/llvm-dev-ARM-Peephole-optimization-instructions-tst-add-tp133109.html

Patch by Pavel Kosov.

Differential Revision: https://reviews.llvm.org/D71701