[all-commits] [llvm/llvm-project] c5ce6d: [X86] Add test to show incorrect ordering of flt.r...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c5ce6d8b561a5b2790a56803df24f800df7a76a8
      https://github.com/llvm/llvm-project/commit/c5ce6d8b561a5b2790a56803df24f800df7a76a8
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-02-25 (Tue, 25 Feb 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/flt-rounds.ll

  Log Message:
  -----------
  [X86] Add test to show incorrect ordering of flt.rounds intrinsic relative to calls to fesetround.

We don't order flt.rounds intrinsics relative to side effecting
operations in SelectionDAG. And we CSE multiple calls because of
this.