[all-commits] [llvm/llvm-project] 11e3dd: GlobalISel: Reimplement fewerElementsVectorBasic

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 11e3dde6252f481238dccd14956350ff328c4087
      https://github.com/llvm/llvm-project/commit/11e3dde6252f481238dccd14956350ff328c4087
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-24 (Mon, 24 Feb 2020)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

  Log Message:
  -----------
  GlobalISel: Reimplement fewerElementsVectorBasic

Changes the handling of odd breakdowns, and avoids using
G_EXTRACT/G_INSERT. Pad with undef to a wider size, and unmerge. Also
avoid introducing instructions for the fully undef components.