[all-commits] [llvm/llvm-project] a5424d: [AVR] Use correct register class for mul instructions

[Ayke via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a5424ded377ea5aeedf6de2a9293e4d1b3da02be
      https://github.com/llvm/llvm-project/commit/a5424ded377ea5aeedf6de2a9293e4d1b3da02be
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-02-24 (Mon, 24 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AVR/AVRInstrInfo.td

  Log Message:
  -----------
  [AVR] Use correct register class for mul instructions

A number of multiplication instructions (muls, mulsu, fmul, fmuls,
fmulsu) had the wrong register class for an operand. This resulted in
the wrong register being used for the instruction.

Example:

    target datalayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8"
    target triple = "avr-atmel-none"

    define i16 @sliceAppend(i16, i16, i16, i16, i16, i16) addrspace(1) {
      %d = mul i16 %0, %5
      ret i16 %d
    }

The first instruction would be muls r24, r31 before this patch. The r31
should have been r15 if you look at the intermediate forms during
instruction selection / register allocation, but the generated
instruction uses r31. After this patch, an extra movw is inserted to get
%5 in range for muls.

To make sure this bug is fixed everywhere, I checked all instructions
and found that most multiplication instructions suffered from this bug,
which I have fixed with this patch. No other instructions appear to be
affected.

Differential Revision: https://reviews.llvm.org/D74281