[all-commits] [llvm/llvm-project] 7efabe: [MIR][ARM] MachineOperand comments
sjoerdmeijer via All-commits
all-commits at lists.llvm.org
Mon Feb 24 06:20:48 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 7efabe5c7de46fe190638741c6ee81ae13255e38
https://github.com/llvm/llvm-project/commit/7efabe5c7de46fe190638741c6ee81ae13255e38
Author: Sjoerd Meijer <sjoerd.meijer at arm.com>
Date: 2020-02-24 (Mon, 24 Feb 2020)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
M llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
M llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-fp-const.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-pic.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-ropi-rwpi.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir
M llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
M llvm/test/CodeGen/ARM/cmpxchg.mir
M llvm/test/CodeGen/ARM/codesize-ifcvt.mir
M llvm/test/CodeGen/ARM/constant-island-movwt.mir
M llvm/test/CodeGen/ARM/constant-islands-cfg.mir
M llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
M llvm/test/CodeGen/ARM/expand-pseudos.mir
M llvm/test/CodeGen/ARM/fpoffset_overflow.mir
M llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
M llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
M llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
M llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
M llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
M llvm/test/CodeGen/ARM/ifcvt_triangleSameCvtNext.mir
M llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
M llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
M llvm/test/CodeGen/ARM/load_store_opt_kill.mir
M llvm/test/CodeGen/ARM/load_store_opt_reg_limit.mir
M llvm/test/CodeGen/ARM/machine-copyprop.mir
M llvm/test/CodeGen/ARM/peephole-phi.mir
M llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
M llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
M llvm/test/CodeGen/ARM/tail-dup-bundle.mir
M llvm/test/CodeGen/ARM/tst-peephole.mir
M llvm/test/CodeGen/ARM/vldm-liveness.mir
M llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir
M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
M llvm/test/CodeGen/Thumb/peephole-cmp.mir
M llvm/test/CodeGen/Thumb/peephole-mi.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir
M llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
M llvm/test/CodeGen/Thumb2/high-reg-spill.mir
M llvm/test/CodeGen/Thumb2/ifcvt-cbz.mir
M llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir
M llvm/test/CodeGen/Thumb2/peephole-addsub.mir
M llvm/test/CodeGen/Thumb2/peephole-cmp.mir
M llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir
M llvm/test/CodeGen/Thumb2/t2sizereduction.mir
M llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir
Log Message:
-----------
[MIR][ARM] MachineOperand comments
This adds infrastructure to print and parse MIR MachineOperand comments.
The motivation for the ARM backend is to print condition code names instead of
magic constants that are difficult to read (for human beings). For example,
instead of this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
t2Bcc %bb.4, 0, killed $cpsr
we now print this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg
t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr
This shows that MachineOperand comments are enclosed between /* and */. In this
example, the EOR instruction is not conditionally executed (i.e. it is "always
executed"), which is encoded by the 14 immediate machine operand. Thus, now
this machine operand has /* CC::always */ as a comment. The 0 on the next
conditional branch instruction represents the equal condition code, thus now
this operand has /* CC:eq */ as a comment.
As it is a comment, the MI lexer/parser completely ignores it. The benefit is
that this keeps the change in the lexer extremely minimal and no target
specific parsing needs to be done. The changes on the MIPrinter side are also
minimal, as there is only one target hooks that is used to create the machine
operand comments.
Differential Revision: https://reviews.llvm.org/D74306
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