[all-commits] [llvm/llvm-project] 86c52a: [TargetLowering] SimplifyDemandedBits - use getVal...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 86c52af05a64c4aa9d61984eeda8fb7849a4b0fa
      https://github.com/llvm/llvm-project/commit/86c52af05a64c4aa9d61984eeda8fb7849a4b0fa
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-02-21 (Fri, 21 Feb 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  Log Message:
  -----------
  [TargetLowering] SimplifyDemandedBits - use getValidShiftAmountConstant helper.

Use the SelectionDAG::getValidShiftAmountConstant helper to get const/constsplat shift amounts, which allows us to drop the out of range shift amount early-out.

First step towards better non-uniform shift amount support in SimplifyDemandedBits.


  Commit: d33e96b68c6f6424dc81145b1301f4cd478e84a2
      https://github.com/llvm/llvm-project/commit/d33e96b68c6f6424dc81145b1301f4cd478e84a2
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-02-21 (Fri, 21 Feb 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/h-register-addressing-32.ll
    M llvm/test/CodeGen/X86/h-register-addressing-64.ll

  Log Message:
  -----------
  [X86] Regenerate hi reg tests


Compare: https://github.com/llvm/llvm-project/compare/35b685270b41...d33e96b68c6f