[all-commits] [llvm/llvm-project] b1d474: [Hexagon] Change HVX vector predicate types from v...

[Krzysztof Parzyszek via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b1d47467e26142e6029e9ec7ca5c42645ffaa7bb
      https://github.com/llvm/llvm-project/commit/b1d47467e26142e6029e9ec7ca5c42645ffaa7bb
  Author: Krzysztof Parzyszek <kparzysz at quicinc.com>
  Date:   2020-02-19 (Wed, 19 Feb 2020)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsHexagon.def
    M clang/include/clang/Basic/BuiltinsHexagonDep.def
    A clang/include/clang/Basic/BuiltinsHexagonMapCustomDep.def
    M clang/include/clang/module.modulemap
    M clang/lib/Basic/Targets/Hexagon.h
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/test/CodeGen/builtins-hexagon-v66-128B.c
    M clang/test/CodeGen/builtins-hexagon-v66.c
    M clang/test/CodeGen/builtins-hvx128.c
    M clang/test/CodeGen/builtins-hvx64.c
    M llvm/include/llvm/IR/IntrinsicsHexagon.td
    M llvm/include/llvm/IR/IntrinsicsHexagonDep.td
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
    M llvm/lib/Target/Hexagon/HexagonIntrinsics.td
    M llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
    M llvm/lib/Target/Hexagon/HexagonSubtarget.h
    M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
    M llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll
    M llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
    M llvm/test/CodeGen/Hexagon/early-if-vecpred.ll
    M llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
    M llvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll
    M llvm/test/CodeGen/Hexagon/hvx-byte-store.ll
    M llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll
    M llvm/test/CodeGen/Hexagon/hvx-dual-output.ll
    M llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
    M llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll
    M llvm/test/CodeGen/Hexagon/intrinsics-v60-alu.ll
    M llvm/test/CodeGen/Hexagon/intrinsics-v60-misc.ll
    M llvm/test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll
    M llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
    M llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll
    M llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
    M llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll
    M llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
    M llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
    M llvm/test/CodeGen/Hexagon/intrinsics/v65.ll
    M llvm/test/CodeGen/Hexagon/late_instr.ll
    M llvm/test/CodeGen/Hexagon/peephole-move-phi.ll
    M llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll
    M llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll
    M llvm/test/CodeGen/Hexagon/reg-scavengebug-4.ll
    M llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll
    M llvm/test/CodeGen/Hexagon/split-vecpred.ll
    M llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
    M llvm/test/CodeGen/Hexagon/swp-sigma.ll
    M llvm/test/CodeGen/Hexagon/v6-inlasm4.ll
    M llvm/test/CodeGen/Hexagon/v6-spill1.ll
    M llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll
    M llvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll
    M llvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll
    M llvm/test/CodeGen/Hexagon/v60-vsel1.ll
    M llvm/test/CodeGen/Hexagon/v60-vsel2.ll
    M llvm/test/CodeGen/Hexagon/v60Intrins.ll
    M llvm/test/CodeGen/Hexagon/v60_sort16.ll
    M llvm/test/CodeGen/Hexagon/v60small.ll
    M llvm/test/CodeGen/Hexagon/v62-inlasm4.ll
    M llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll
    M llvm/test/CodeGen/Hexagon/v6vect-pred2.ll
    M llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll
    M llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
    M llvm/test/CodeGen/Hexagon/vecPred2Vec.ll
    M llvm/test/CodeGen/Hexagon/vect-downscale.ll
    M llvm/test/CodeGen/Hexagon/vector-align.ll
    M llvm/test/CodeGen/Hexagon/vselect-pseudo.ll

  Log Message:
  -----------
  [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1

This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.

It may cause existing bitcode files to become invalid.

* Converting between vector predicates and vector registers must be
  done explicitly via vandvrt/vandqrt instructions (their intrinsics),
  i.e. (for 64-byte mode):
    %Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
    %V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)

  The conversion intrinsics are:
    declare  <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
    declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
    declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
    declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
  They are all pure.

* Vector predicate values cannot be loaded/stored directly. This directly
  reflects the architecture restriction. Loading and storing or vector
  predicates must be done indirectly via vector registers and explicit
  conversions via vandvrt/vandqrt instructions.