[all-commits] [llvm/llvm-project] fceb3e: [ARM] MVE VADDLV lowering

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fceb3e3b4aec635d4e31dda618c7e4c17516cdb9
      https://github.com/llvm/llvm-project/commit/fceb3e3b4aec635d4e31dda618c7e4c17516cdb9
  Author: David Green <david.green at arm.com>
  Date:   2020-02-19 (Wed, 19 Feb 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll

  Log Message:
  -----------
  [ARM] MVE VADDLV lowering

Following on from the extra VADDV lowering, this extends things to
handle VADDLV which allows summing values into a pair of i32 registers,
together treated as a i64. This needs to be done in DAGCombine too as
the types are otherwise illegal, which is a fairly simple addition on
top of the existing code.

There is also a VADDLVA instruction handled here, that adds the incoming
values from the two general purpose registers. As opposed to the
non-long version where we could just add patterns for add(x, VADDV), the
long version needs to handle this early before the i64 has being split
into too many pieces.

Differential Revision: https://reviews.llvm.org/D74224