[all-commits] [llvm/llvm-project] 90dc78: [ARM, MVE] Add intrinsics for abs, neg and not oper...
Simon Tatham via All-commits
all-commits at lists.llvm.org
Tue Feb 18 01:36:33 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 90dc78bc62784faaa55afb0320cf3c2187d80ac6
https://github.com/llvm/llvm-project/commit/90dc78bc62784faaa55afb0320cf3c2187d80ac6
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/arm-mve-intrinsics/absneg.c
Log Message:
-----------
[ARM,MVE] Add intrinsics for abs, neg and not operations.
Summary:
This commit adds the unpredicated intrinsics for the unary operations
vabsq (absolute value), vnegq (arithmetic negation), vmvnq (bitwise
complement), vqabsq and vqnegq (saturating versions of abs and neg for
signed integers, in the sense that they give INT_MAX if an input lane
is INT_MIN).
This is done entirely in clang: all of these operations have existing
isel patterns and existing tests for them on the LLVM side, so I've
just made clang emit the same IR that those patterns already match.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: MarkMurrayARM
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74331
Commit: df3ed6c0fe31094941e4cd814cdf924b63993c4e
https://github.com/llvm/llvm-project/commit/df3ed6c0fe31094941e4cd814cdf924b63993c4e
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
Log Message:
-----------
[ARM,MVE] Add intrinsics for int <-> float conversion.
Summary:
This adds the unpredicated versions of the family of vcvtq intrinsics
that convert between a vector of floats and a vector of the same size
of integer. These are represented in IR using the standard fptosi,
fptoui, sitofp and uitofp operations, which existing LLVM codegen
already handles.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: MarkMurrayARM
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74332
Commit: c8b3196e54308b0113d2a0888d13ccc92e3b7ccc
https://github.com/llvm/llvm-project/commit/c8b3196e54308b0113d2a0888d13ccc92e3b7ccc
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
A clang/test/CodeGen/arm-mve-intrinsics/vrnd.c
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
A llvm/test/CodeGen/Thumb2/mve-intrinsics/vrintn.ll
Log Message:
-----------
[ARM,MVE] Add intrinsics for FP rounding operations.
Summary:
This adds the unpredicated forms of six different MVE intrinsics which
all round a vector of floating-point numbers to integer values,
leaving them still in FP format, differing only in rounding mode and
exception settings.
Five of them map to existing target-independent intrinsics in LLVM IR,
such as @llvm.trunc and @llvm.rint. The sixth, mapping to the `vrintn`
instruction, is done by inventing a target-specific intrinsic.
(`vrintn` behaves the same as `vrintx` in terms of the output value:
the side effects on the FPSCR flags are the only difference between
the two. But ACLE specifies separate user-callable intrinsics for the
two, so the side effects matter enough to make sure we generate the
right one of the two instructions in each case.)
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: miyuki
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74333
Commit: b6236e94799e43fad1f024e84ed56a85d9a3623f
https://github.com/llvm/llvm-project/commit/b6236e94799e43fad1f024e84ed56a85d9a3623f
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/arm-mve-intrinsics/vrev.c
Log Message:
-----------
[ARM,MVE] Add the vrev16q, vrev32q, vrev64q family.
Summary:
These intrinsics just reorder the lanes of a vector, so the natural IR
representation is as a shufflevector operation. Existing LLVM codegen
already recognizes those particular shufflevectors and generates the
MVE VREV instruction.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74334
Commit: 68b49f7ef49eec068b7ddcf86c868e2a193e64e1
https://github.com/llvm/llvm-project/commit/68b49f7ef49eec068b7ddcf86c868e2a193e64e1
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
A clang/test/CodeGen/arm-mve-intrinsics/vclz.c
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
A llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll
Log Message:
-----------
[ARM,MVE] Add intrinsics vclzq and vclsq.
Summary:
vclzq maps nicely to the existing target-independent @llvm.ctlz IR
intrinsic. But vclsq ('count leading sign bits') has no corresponding
target-independent intrinsic, so I've made up @llvm.arm.mve.vcls.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: miyuki
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74335
Commit: 9dcc1667abfc49bf6d44688a02e12cd96244ea72
https://github.com/llvm/llvm-project/commit/9dcc1667abfc49bf6d44688a02e12cd96244ea72
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstrNEON.td
Log Message:
-----------
[ARM] Allow `ARMVectorRegCast` to match bitconverts too. (NFC)
Summary:
When we start putting instances of `ARMVectorRegCast` in complex isel
patterns, it will be awkward that they're often turned into the more
standard `bitconvert` in little-endian mode. We'd rather not have to
write separate isel patterns for the two endiannesses, matching
different but equivalent cast operations.
This change aims to fix that awkwardness in advance, by turning the
Tablegen record `ARMVectorRegCast` from a simple `SDNode` instance
into a `PatFrags` that can match either kind of cast – with a
predicate that prevents it matching a bitconvert in the big-endian
case, where bitconvert isn't semantically identical.
No existing code generation should be affected by this change, but it
will enable the patterns introduced by D74336 to work in both
endiannesses.
Reviewers: dmgreen
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74716
Commit: 5e97940cd27961a0b872ff551fc98135507288b3
https://github.com/llvm/llvm-project/commit/5e97940cd27961a0b872ff551fc98135507288b3
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
M llvm/lib/Target/ARM/ARMInstrMVE.td
A llvm/test/CodeGen/Thumb2/mve-intrinsics/vmovl.ll
M llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
Log Message:
-----------
[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.
Summary:
These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.
Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.
The output of one existing codegen test is improved by those new
rules.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74336
Commit: c32af4447f79f5e7f246917fe1c3f58b2f6fc2a6
https://github.com/llvm/llvm-project/commit/c32af4447f79f5e7f246917fe1c3f58b2f6fc2a6
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2020-02-18 (Tue, 18 Feb 2020)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
M clang/utils/TableGen/MveEmitter.cpp
M llvm/lib/Target/ARM/ARMInstrMVE.td
A llvm/test/CodeGen/Thumb2/mve-intrinsics/vmovn.ll
Log Message:
-----------
[ARM,MVE] Add the vmovnbq,vmovntq intrinsic family.
Summary:
These are in some sense the inverse of vmovl[bt]q: they take a vector
of n wide elements and truncate each to half its width. So they only
write half a vector's worth of output data, and therefore they also
take an 'inactive' parameter to provide the other half of the data in
the output vector. So vmovnb overwrites the even lanes of 'inactive'
with the narrowed values from the main input, and vmovnt overwrites
the odd lanes.
LLVM had existing codegen which generates these MVE instructions in
response to IR that takes two vectors of wide elements, or two vectors
of narrow ones. But in this case, we have one vector of each. So my
clang codegen strategy is to narrow the input vector of wide elements
by simply reinterpreting it as the output type, and then we have two
narrow vectors and can represent the operation as a vector shuffle
that interleaves lanes from both of them.
Even so, not all the cases I needed ended up being selected as a
single MVE instruction, so I've added a couple more patterns that spot
combinations of the 'MVEvmovn' and 'ARMvrev32' SDNodes which can be
generated as a VMOVN instruction with operands swapped.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74337
Compare: https://github.com/llvm/llvm-project/compare/f14680ce2966...c32af4447f79
More information about the All-commits
mailing list