[all-commits] [llvm/llvm-project] bf3b86: [Hexagon] v67+ HVX register pairs should support e...

[androm3da via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bf3b86bc2f1020fc1b3a69803e6c3df7ffe8694d
      https://github.com/llvm/llvm-project/commit/bf3b86bc2f1020fc1b3a69803e6c3df7ffe8694d
  Author: Brian Cain <bcain at codeaurora.org>
  Date:   2020-02-14 (Fri, 14 Feb 2020)

  Changed paths:
    M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
    M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
    M llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
    M llvm/test/CodeGen/Hexagon/swp-sigma.ll
    A llvm/test/CodeGen/Hexagon/vect-regpairs.ll
    A llvm/test/MC/Hexagon/hvx-swapped-regpairs-alias-neg.s
    A llvm/test/MC/Hexagon/hvx-swapped-regpairs.s

  Log Message:
  -----------
  [Hexagon] v67+ HVX register pairs should support either direction

Assembler now permits pairs like 'v0:1', which are encoded
differently from the odd-first pairs like 'v1:0'.

The compiler will require more work to leverage these new register
pairs.