[all-commits] [llvm/llvm-project] b6a9fe: [AArch64] Add BIT/BIF support.

[Pavel Iliin via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b6a9fe209992789be3ed95664d25196361cfad34
      https://github.com/llvm/llvm-project/commit/b6a9fe209992789be3ed95664d25196361cfad34
  Author: Pavel Iliin <Pavel.Iliin at arm.com>
  Date:   2020-02-14 (Fri, 14 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SchedA57.td
    M llvm/lib/Target/AArch64/AArch64SchedCyclone.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
    M llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    A llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
    A llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
    M llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
    M llvm/test/CodeGen/AArch64/sat-add.ll
    M llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
    M llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
    M llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll

  Log Message:
  -----------
  [AArch64] Add BIT/BIF support.

This patch added generation of SIMD bitwise insert BIT/BIF instructions.
In the absence of GCC-like functionality for optimal constraints satisfaction
during register allocation the bitwise insert and select patterns are matched
by pseudo bitwise select BSP instruction with not tied def.
It is expanded later after register allocation with def tied
to BSL/BIT/BIF depending on operands registers.
This allows to get rid of redundant moves.

Reviewers: t.p.northover, samparker, dmgreen

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D74147