[all-commits] [llvm/llvm-project] de7161: PPC: Prepare tests for switch of default denormal-...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: de716173357f5715fe14788ec022e6eeb2b33540
      https://github.com/llvm/llvm-project/commit/de716173357f5715fe14788ec022e6eeb2b33540
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-12 (Wed, 12 Feb 2020)

  Changed paths:
    M llvm/test/CodeGen/PowerPC/fmf-propagation.ll
    M llvm/test/CodeGen/PowerPC/qpx-recipest.ll
    M llvm/test/CodeGen/PowerPC/recipest.ll

  Log Message:
  -----------
  PPC: Prepare tests for switch of default denormal-fp-math

These tests fail when the default is switched to assume IEEE denormal
handling. I'm not sure if PPC really has a way to control the denormal
input handling.


  Commit: e174c278ca2f91bd2cae4fc849ba888fa7f851a9
      https://github.com/llvm/llvm-project/commit/e174c278ca2f91bd2cae4fc849ba888fa7f851a9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-12 (Wed, 12 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result

When SI_IF is inserted, it constrains the source register with a
register class, which was quite likely a G_ICMP. This was incorrectly
treating it as a scalar, and then applyMappingImpl would end up
producing invalid MIR since this was unexpected.

Also fix not using all VGPR sources for vcc outputs.


  Commit: 045a8921d74d99e21b454ee8ef4f97d6c81b8cc1
      https://github.com/llvm/llvm-project/commit/045a8921d74d99e21b454ee8ef4f97d6c81b8cc1
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-12 (Wed, 12 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Select G_CTLZ_ZERO_UNDEF

Directly select this rather than going through the intermediate
instruction, which may provide some combine value in the future.


  Commit: d1b393d92c2d595ee5893c8e9ebc9da50d15f2a0
      https://github.com/llvm/llvm-project/commit/d1b393d92c2d595ee5893c8e9ebc9da50d15f2a0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-12 (Wed, 12 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Select G_CTTZ_ZERO_UNDEF

Directly select this rather than going through the intermediate
instruction, which may provide some combine value in the future.


Compare: https://github.com/llvm/llvm-project/compare/a4384c756bd8...d1b393d92c2d