[all-commits] [llvm/llvm-project] 45417b: [AArch64][GlobalISel] Properly implement widening ...

[Jessica Paquette via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 45417b7aa7fcdd2aa75c1c809a3c7fb3292134be
      https://github.com/llvm/llvm-project/commit/45417b7aa7fcdd2aa75c1c809a3c7fb3292134be
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2020-02-12 (Wed, 12 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Properly implement widening for TB(N)Z

When we have to widen to a 64-bit register, we have to emit a SUBREG_TO_REG.

Add a general-purpose widening helpe  which emits the correct SUBREG_TO_REG
instruction based off of a desired size and add a testcase.

Also remove some asserts which are technically incorrect in `emitTestBit`.

- p0 doesn't count as a scalar type, so we need to check `!Ty.isVector()`
instead

- Whenever we have a s1, the Size/Bit checks are too conservative, so just
remove them

Replace these asserts with less conservative ones where applicable.

Differential Revision: https://reviews.llvm.org/D74427