[all-commits] [llvm/llvm-project] fa61e2: AMDGPU/GlobalISel: Widen non-power-of-2 load results

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fa61e200e53aaa929276abd76482a15c7a9638b7
      https://github.com/llvm/llvm-project/commit/fa61e200e53aaa929276abd76482a15c7a9638b7
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-12 (Wed, 12 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Widen non-power-of-2 load results

Load extra bits if suitably aligned. This allows using widened
3-vector loads on SI, and fixes legalization for <9 x s32> (which LSV
apparently forms frequently on lowered kernel argument lists).

Fix incorrectly treating these as legal on SI. This should emit a
64-bit store and a 32-bit store.

I think all of the load and store rules are just about complete, but
due for a rewrite.