[all-commits] [llvm/llvm-project] 61ca99: [Hexagon] Don't generate short vectors in ISD::SEL...

[Krzysztof Parzyszek via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 61ca996e79bbde58623320ea1f35423ef8a0aa64
      https://github.com/llvm/llvm-project/commit/61ca996e79bbde58623320ea1f35423ef8a0aa64
  Author: Krzysztof Parzyszek <kparzysz at quicinc.com>
  Date:   2020-02-11 (Tue, 11 Feb 2020)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    A llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll

  Log Message:
  -----------
  [Hexagon] Don't generate short vectors in ISD::SELECT in preprocessing

Selection DAG preprocessing runs long after legalization, so make sure
that the types can be handled by the selection code.