[all-commits] [llvm/llvm-project] d7de7a: [X86] Raise the latency for VectorImul from 4 to 5...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d7de7ac370181ec0acb42fa2e4085c870868c4e0
      https://github.com/llvm/llvm-project/commit/d7de7ac370181ec0acb42fa2e4085c870868c4e0
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-02-11 (Tue, 11 Feb 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-mmx.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse41.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-ssse3.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-mmx.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse41.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-ssse3.s

  Log Message:
  -----------
  [X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models

Based on uops.info these should have 5 cycle latency as they did on Haswell/Broadwell. I have no additional internal information from Intel.

This was also shown as a discrepancy in the spreadsheet that was sent with an early llvm-dev post about llvm-exegesis.
It also matches Agner Fog.

Differential Revision: https://reviews.llvm.org/D74357