[all-commits] [llvm/llvm-project] 29bc5d: [BPF] implement isTruncateFree and isZExtFree in B...

[yonghong-song via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 29bc5dd19407c4d7cad1c059dea26ee216ddc7ca
      https://github.com/llvm/llvm-project/commit/29bc5dd19407c4d7cad1c059dea26ee216ddc7ca
  Author: Yonghong Song <yhs at fb.com>
  Date:   2020-02-11 (Tue, 11 Feb 2020)

  Changed paths:
    M llvm/lib/Target/BPF/BPFISelLowering.cpp
    M llvm/lib/Target/BPF/BPFISelLowering.h
    M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll
    M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll
    A llvm/test/CodeGen/BPF/is_trunc_free.ll
    A llvm/test/CodeGen/BPF/is_zext_free.ll

  Log Message:
  -----------
  [BPF] implement isTruncateFree and isZExtFree in BPFTargetLowering

Currently, isTruncateFree() and isZExtFree() callbacks return false
as they are not implemented in BPF backend. This may cause suboptimal
code generation. For example, if the load in the context of zero extension
has more than one use, the pattern zextload{i8,i16,i32} will
not be generated. Rather, the load will be matched first and
then the result is zero extended.

For example, in the test together with this commit, we have
   I1: %0 = load i32, i32* %data_end1, align 4, !tbaa !2
   I2: %conv = zext i32 %0 to i64
   ...
   I3: %2 = load i32, i32* %data, align 4, !tbaa !7
   I4: %conv2 = zext i32 %2 to i64
   ...
   I5: %4 = trunc i64 %sub.ptr.lhs.cast to i32
   I6: %conv13 = sub i32 %4, %2
   ...

The I1 and I2 will match to one zextloadi32 DAG node, where SUBREG_TO_REG is
used to convert a 32bit register to 64bit one. During code generation,
SUBREG_TO_REG is a noop.

The %2 in I3 is used in both I4 and I6. If isTruncateFree() is false,
the current implementation will generate a SLL_ri and SRL_ri
for the zext part during lowering.

This patch implement isTruncateFree() in the BPF backend, so for the
above example, I3 and I4 will generate a zextloadi32 DAG node with
SUBREG_TO_REG is generated during lowering to Machine IR.

isZExtFree() is also implemented as it should help code gen as well.

This patch also enables the change in https://reviews.llvm.org/D73985
since it won't kick in generates MOV_32_64 machine instruction.

Differential Revision: https://reviews.llvm.org/D74101