[all-commits] [llvm/llvm-project] 798305: [X86] Custom lower ISD::FP16_TO_FP and ISD::FP_TO_...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 798305d29b780584a2805bc1002b410b3d703197
      https://github.com/llvm/llvm-project/commit/798305d29b780584a2805bc1002b410b3d703197
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-02-10 (Mon, 10 Feb 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/test/CodeGen/X86/avx512-insert-extract.ll
    M llvm/test/CodeGen/X86/avx512-vec-cmp.ll
    M llvm/test/CodeGen/X86/cvt16.ll
    M llvm/test/CodeGen/X86/half.ll
    M llvm/test/CodeGen/X86/pr31088.ll
    M llvm/test/CodeGen/X86/vector-half-conversions.ll

  Log Message:
  -----------
  [X86] Custom lower ISD::FP16_TO_FP and ISD::FP_TO_FP16 on f16c targets instead of using isel patterns.

We need to use vector instructions for these operations. Previously
we handled this with isel patterns that used extra instructions
and copies to handle the the conversions.

Now we use custom lowering to emit the conversions. This allows
them to be pattern matched and optimized on their own. For
example we can now emit vpextrw to store the result if its going
directly to memory.

I've forced the upper elements to VCVTPHS2PS to zero to keep some
code similar. Zeroes will be needed for strictfp. I've added a
DAG combine for (fp16_to_fp (fp_to_fp16 X)) to avoid extra
instructions in between to be closer to the previous codegen.

This is a step towards strictfp support for f16 conversions.