[all-commits] [llvm/llvm-project] 26bf87: [PowerPC] Fix spilling of vector registers in PEI ...

[Nemanja Ivanovic via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 26bf877ec5ce07eaaf2ebf19e78f26fa59a8e41a
      https://github.com/llvm/llvm-project/commit/26bf877ec5ce07eaaf2ebf19e78f26fa59a8e41a
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2020-02-07 (Fri, 07 Feb 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.h
    M llvm/test/CodeGen/PowerPC/CSR-fit.ll
    M llvm/test/CodeGen/PowerPC/reg-scavenging.ll
    M llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll

  Log Message:
  -----------
  [PowerPC] Fix spilling of vector registers in PEI of EH aware functions

On little endian targets prior to Power9, we spill vector registers using a
swapping store (i.e. stdxvd2x saves the vector with the two doublewords in
big endian order regardless of endianness). This is generally not a problem
since we restore them using the corresponding swapping load (lxvd2x). However
if the restore is done by the unwinder, the vector register contains data in
the incorrect order.

This patch fixes that by using Altivec loads/stores for vector saves and
restores in PEI (which keep the order correct) under those specific conditions:
- EH aware function
- Subtarget requires swaps for VSX memops (Little Endian prior to Power9)

Differential revision: https://reviews.llvm.org/D73692