[all-commits] [llvm/llvm-project] a25310: [AArch64] Predictably disassemble system registers...

[Momchil Velikov via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a2531081b3855ba8c60b340c1721e91d7288cfde
      https://github.com/llvm/llvm-project/commit/a2531081b3855ba8c60b340c1721e91d7288cfde
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2020-02-07 (Fri, 07 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/test/MC/AArch64/ete-sysregs.s
    M llvm/test/MC/AArch64/trace-regs.s
    M llvm/test/MC/Disassembler/AArch64/ete.txt
    M llvm/test/MC/Disassembler/AArch64/trace-regs.txt

  Log Message:
  -----------
  [AArch64] Predictably disassemble system registers with the same encoding

The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers,
defined by separate extension specifications (ETM and ETE,
respectively), yet they use the same encoding in MSR/MRS.

When performing a system register lookup by encoding, we would
essentially return a random one, depending on the number, relative
position in the TableGen file, whether the TableGen records for system
registers are named or not, and, if they are named, depending on
record (not register!) name as well.

This patch works around the issue by explictly checking for the
TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR.

Differential Revision: https://reviews.llvm.org/D74074