[all-commits] [llvm/llvm-project] cacc3b: [AMDGPU] Cleanup assumptions about generated subregs

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: cacc3b7a557af837a3ae01cd085e3d435aae6e1f
      https://github.com/llvm/llvm-project/commit/cacc3b7a557af837a3ae01cd085e3d435aae6e1f
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2020-02-06 (Thu, 06 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
    M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
    M llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

  Log Message:
  -----------
  [AMDGPU] Cleanup assumptions about generated subregs

We are using countPopulation on a LaneBitmask to determine
a number of registers it covers. This is the assumption which
does not necessarily need to be true. It is not changed but
factored into a single call SIRegisterInfo::getNumCoveredRegs().

Some other places are cleaned up with respect to assumptions
about subreg indexes values and tablegen behavior.

Differential Revision: https://reviews.llvm.org/D74177