[all-commits] [llvm/llvm-project] d78cef: [AArch64][GlobalISel] Emit TBZ for SGT cond branch...

[Jessica Paquette via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d78cefb1601070cb028b61bbc1bd6f25a9c1837c
      https://github.com/llvm/llvm-project/commit/d78cefb1601070cb028b61bbc1bd6f25a9c1837c
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2020-02-06 (Thu, 06 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Emit TBZ for SGT cond branches against -1

When we have a G_BRCOND fed by a sgt compare against -1, we can just emit a TBZ.

This is similar to the code in `AArch64TargetLowering::LowerBR_CC`.

Also while we're here, properly scope the commutative constant check in
`selectCompareBranch`, since it sometimes would call
`getConstantVRegValWithLookThrough` twice.

Differential Revision: https://reviews.llvm.org/D74149