[all-commits] [llvm/llvm-project] c6bdd8: [X86] Improve the gather scheduler models for Skyl...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c6bdd8e73110e14dc54833137cecef9c07d2dc24
      https://github.com/llvm/llvm-project/commit/c6bdd8e73110e14dc54833137cecef9c07d2dc24
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-02-05 (Wed, 05 Feb 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
    M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512vl.s

  Log Message:
  -----------
  [X86] Improve the gather scheduler models for SkylakeClient and SkylakeServer

The load ports need a cycle for each potentially loaded element just like Haswell and Skylake. Unlike Haswell and Broadwell, the number of uops does not scale with the number of elements. Instead the load uops run for multiple cycles.

I've taken the latency number from the uops.info. The port binding for the non-load uops is taken from the original IACA data I have.

Differential Revision: https://reviews.llvm.org/D74000