[all-commits] [llvm/llvm-project] 0b8a54: [AArch64][ARM] Always expand ordered vector reduct...

[David Green via All-commits]

  Branch: refs/heads/release/10.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 0b8a540dff86662fc9426bb4dd8797c547db5000
      https://github.com/llvm/llvm-project/commit/0b8a540dff86662fc9426bb4dd8797c547db5000
  Author: Nikita Popov <nikita.ppv at gmail.com>
  Date:   2020-02-05 (Wed, 05 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    A llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
    A llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
    A llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
    A llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
    A llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll

  Log Message:
  -----------
  [AArch64][ARM] Always expand ordered vector reductions (PR44600)

fadd/fmul reductions without reassoc are lowered to
VECREDUCE_STRICT_FADD/FMUL nodes, which don't have legalization
support. Until that is in place, expand these intrinsics on
ARM and AArch64. Other targets always expand the vector reduction
intrinsics.

Additionally expand fmax/fmin reductions without nonan flag on
AArch64, as the backend asserts that the flag is present when
lowering VECREDUCE_FMIN/FMAX.

This fixes https://bugs.llvm.org/show_bug.cgi?id=44600.

Differential Revision: https://reviews.llvm.org/D73135

(cherry picked from commit 70d345e687caba4ac1f95655c6924dfa91e0083f)


  Commit: 99c6a4ea9201f09e8107bb83675f1e7235456b6d
      https://github.com/llvm/llvm-project/commit/99c6a4ea9201f09e8107bb83675f1e7235456b6d
  Author: Nikita Popov <nikita.ppv at gmail.com>
  Date:   2020-02-05 (Wed, 05 Feb 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    A llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll

  Log Message:
  -----------
  [ARM] Expand vector reduction intrinsics on soft float

Followup to D73135. If the target doesn't have hard float (default
for ARM), then we assert when trying to soften the result of vector
reduction intrinsics. This patch marks these for expansion as well.
(A bit odd to use vectors on a target without hard float ... but
that's where you end up if you expose target-independent vector types.)

Differential Revision: https://reviews.llvm.org/D73854

(cherry picked from commit 1cc4f8d17247cd9be88addd75d060f9321b6f8b0)


  Commit: 8195a96595baca8c0141de2a121dcf3f8c0ea616
      https://github.com/llvm/llvm-project/commit/8195a96595baca8c0141de2a121dcf3f8c0ea616
  Author: David Green <david.green at arm.com>
  Date:   2020-02-05 (Wed, 05 Feb 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
    A llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

  Log Message:
  -----------
  [ARM][VecReduce] Force expand vector_reduce_fmin

Under MVE, we do not have any lowering for fminimum, which a
vector_reduce_fmin without NoNan will be expanded into. As with the
other recent patches, force this to expand in the pre-isel pass. Note
that Neon lowering would be OK because the scalar fminimum uses the
vector VMIN instruction, but is probably better to just rely on the
scalar operations, which is what is done here.

Also fixes what appears to be the reversal of INF vs -INF in the
vector_reduce_fmin widening code.

(cherry picked from commit 362d00e0510ee75750499e2993a782428e377215)


Compare: https://github.com/llvm/llvm-project/compare/211aa5bf59eb...8195a96595ba