[all-commits] [llvm/llvm-project] 05f2a0: AMDGPU/GlobalISel: Legalize G_SEXT_INREG

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 05f2a04ba7fd4bced5e9c8866888bb91e8cee256
      https://github.com/llvm/llvm-project/commit/05f2a04ba7fd4bced5e9c8866888bb91e8cee256
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-04 (Tue, 04 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Legalize G_SEXT_INREG

Split the VALU 64-bit case in RegBankSelect.


  Commit: 0693e827ed3ce081771366e29f5ece025e42a3d2
      https://github.com/llvm/llvm-project/commit/0693e827ed3ce081771366e29f5ece025e42a3d2
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-04 (Tue, 04 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Do a better job splitting 64-bit G_SEXT_INREG

We don't need to expand to full shifts for the > 32-bit case. This
just switches to a sext_inreg of the high half.


  Commit: 12fe9b26ec88bb2dd40d574a644edca302e804b2
      https://github.com/llvm/llvm-project/commit/12fe9b26ec88bb2dd40d574a644edca302e804b2
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-02-04 (Tue, 04 Feb 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Select G_SEXT_INREG


Compare: https://github.com/llvm/llvm-project/compare/0f116fd9d86d...12fe9b26ec88