[all-commits] [llvm/llvm-project] c7768c: [X86] Update the haswell and broadwell scheduler i...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c7768ce52224297fd5d39e8dae69cf6b0df4ece1
      https://github.com/llvm/llvm-project/commit/c7768ce52224297fd5d39e8dae69cf6b0df4ece1
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx2.s
    M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx2.s

  Log Message:
  -----------
  [X86] Update the haswell and broadwell scheduler information for gather instructions

Broadwell was missing half the gather instructions. Both models
had some mixups in the resource costs and number of uops.

I've updated here based on what I think the original IACA source
says with some cross checking against the microcode.

I'm not sure about latency as the IACA source I have doesn't have
that information. So I'm using the latency from uops.info.

I plan to update Skylake models as well, but I'll do that in a
separate patch.

Differential Revision: https://reviews.llvm.org/D73844