[all-commits] [llvm/llvm-project] 70d345: [AArch64][ARM] Always expand ordered vector reduct...

[Nikita Popov via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 70d345e687caba4ac1f95655c6924dfa91e0083f
      https://github.com/llvm/llvm-project/commit/70d345e687caba4ac1f95655c6924dfa91e0083f
  Author: Nikita Popov <nikita.ppv at gmail.com>
  Date:   2020-01-30 (Thu, 30 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    A llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
    A llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
    A llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
    A llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
    A llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll

  Log Message:
  -----------
  [AArch64][ARM] Always expand ordered vector reductions (PR44600)

fadd/fmul reductions without reassoc are lowered to
VECREDUCE_STRICT_FADD/FMUL nodes, which don't have legalization
support. Until that is in place, expand these intrinsics on
ARM and AArch64. Other targets always expand the vector reduction
intrinsics.

Additionally expand fmax/fmin reductions without nonan flag on
AArch64, as the backend asserts that the flag is present when
lowering VECREDUCE_FMIN/FMAX.

This fixes https://bugs.llvm.org/show_bug.cgi?id=44600.

Differential Revision: https://reviews.llvm.org/D73135