[all-commits] [llvm/llvm-project] dc141a: [GlobalISel] (fix) Use pointer type size for offse...

Thu Jan 30 05:32:42 PST 2020

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: dc141af7553871b94f0d7cb4b1f2096578a923be
      https://github.com/llvm/llvm-project/commit/dc141af7553871b94f0d7cb4b1f2096578a923be
  Author: Dominik Montada <dominik.montada at gmail.com>
  Date:   2020-01-30 (Thu, 30 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  Log Message:
  -----------
  [GlobalISel] (fix) Use pointer type size for offset constant when lowering stores

Commit 9965b12fd1b was supposed to change the offset constant when
lowering load/stores, but only introduced this change for loads. This
patch adds the same fix for stores.

  Commit: d21182d692e8109fdc3af1eb52dd293fbb3e876f
      https://github.com/llvm/llvm-project/commit/d21182d692e8109fdc3af1eb52dd293fbb3e876f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-30 (Thu, 30 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Only map VOP operands to VGPRs

This trivially avoids violating the constant bus restriction.

Previously this was allowing one SGPR in the first source
operand, which technically also avoided violating this for most
operations (but not for special cases reading vcc).

We do need to write some new, smarter operand folds to pick the
optimal SGPR to use in some kind of post-isel fold, but that's purely
an optimization.

I was originally thinking we would pick which operands should be SGPRs
in RegBankSelect, but I think this isn't really manageable. There
would be additional complexity to handle every G_* instruction, and
then any nontrivial instruction patterns would need to know when to
avoid violating it, which is likely to be very error prone.

I think having all inputs being canonically copies to VGPRs will
simplify the operand folding logic. The current folding we do is
backwards, and only considers one operand at a time, relative to
operands it already has. It therefore poorly handles the case where
there is already a constant bus operand user. If all operands are
copies, it's somewhat simpler to consider all input operands at once
to choose the optimal constant bus user.

Since the failure mode for constant bus violations is now a verifier
error and not an selection failure, this moves towards a place where
we can turn on the fallback mode. The SGPR copy folding optimizations
can be left for later.

Compare: https://github.com/llvm/llvm-project/compare/ef465d0ad2b9...d21182d692e8