[all-commits] [llvm/llvm-project] f00be8: [PowerPC][Future] Prefixed Instructions 64 Byte Bo...

[stefanp-ibm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f00be8da62b8169c6548f32834f307bb520e8754
      https://github.com/llvm/llvm-project/commit/f00be8da62b8169c6548f32834f307bb520e8754
  Author: Stefan Pintilie <stefanp at ca.ibm.com>
  Date:   2020-01-30 (Thu, 30 Jan 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt
    A llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
    A llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.h
    A llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s
    A llvm/test/MC/PowerPC/ppc64-prefix-align.s

  Log Message:
  -----------
  [PowerPC][Future] Prefixed Instructions 64 Byte Boundary Support

A known limitation for Future CPU is that the new prefixed instructions may
not cross 64 Byte boundaries.

All instructions are already 4 byte aligned so the only situation where this
can occur is when the prefix is in one 64 byte block and the instruction that
is prefixed is at the top of the next 64 byte block. To fix this case
PPCELFStreamer was added to intercept EmitInstruction. When a prefixed
instruction is emitted we try to align it to 64 Bytes by adding a maximum of
4 bytes. If the prefixed instruction crosses the 64 Byte boundary then the
alignment would trigger and a 4 byte nop would be added to push the
instruction into the next 64 byte block.

Differential Revision: https://reviews.llvm.org/D72570