[all-commits] [llvm/llvm-project] 050cd4: [AArch64][GlobalISel] Fix TBNZ/TBZ opcode selection

[Jessica Paquette via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 050cd443ca7c9dc9da9d2dcdfb4070bee7185c4e
      https://github.com/llvm/llvm-project/commit/050cd443ca7c9dc9da9d2dcdfb4070bee7185c4e
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2020-01-29 (Wed, 29 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Fix TBNZ/TBZ opcode selection

When the bit is <= 32, we have to use the W register variant for TB(N)Z.

This is because of the way the instruction is encoded.

Differential Revision: https://reviews.llvm.org/D73660