[all-commits] [llvm/llvm-project] 68b102: AMDGPU: Directly select 16-bank LDS case of llvm.a...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 68b102b97ac340698e31ab5af0c4394a9789a49c
      https://github.com/llvm/llvm-project/commit/68b102b97ac340698e31ab5af0c4394a9789a49c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-29 (Wed, 29 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
    M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td

  Log Message:
  -----------
  AMDGPU: Directly select 16-bank LDS case of llvm.amdgcn.interp.p1.f16

Manually select this is as a tablegen workraound. Both SelectionDAG
and GlobalISel end up misplacing the copy to m0 when both instructions
in the output need it. Neither considers that both output instructions
depend on m0. I don't know of any other pattern we need to handle this
case, so it's less effort to just workaround this for now.


  Commit: b63629a58d72cb881e79cbabe8a56da90d68ae5b
      https://github.com/llvm/llvm-project/commit/b63629a58d72cb881e79cbabe8a56da90d68ae5b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-29 (Wed, 29 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir

  Log Message:
  -----------
  GlobalISel: Fix mask computation in lowerInsert

This is supposed to be the high bit index, not the width. Use the
wrapping form of getBitsSet and avoid the bitflip.


Compare: https://github.com/llvm/llvm-project/compare/0d7bd343127e...b63629a58d72