[all-commits] [llvm/llvm-project] ac0b9b: AMDPGPU/GlobalISel: Select more MUBUF global addre...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ac0b9b4ccf3e356061f66f54b99588bc71071e73
      https://github.com/llvm/llvm-project/commit/ac0b9b4ccf3e356061f66f54b99588bc71071e73
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-27 (Mon, 27 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir

  Log Message:
  -----------
  AMDPGPU/GlobalISel: Select more MUBUF global addressing modes

The handling of the high bits of the resource descriptor seem weird to
me, where the 3rd dword changes based on the instruction.