[all-commits] [llvm/llvm-project] 8a6b94: [MVE] Fixup order of gather writeback intrinsic ou...

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8a6b948eb59267736a34a5deace9c7d947c63492
      https://github.com/llvm/llvm-project/commit/8a6b948eb59267736a34a5deace9c7d947c63492
  Author: David Green <david.green at arm.com>
  Date:   2020-01-27 (Mon, 27 Jan 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/scatter-gather.ll
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vldr.ll

  Log Message:
  -----------
  [MVE] Fixup order of gather writeback intrinsic outputs

The MVE_VLDRWU32_qi_pre gather loads, like the other _pre/_post mve
loads returns the writeback as result 0, the value as result 1. The llvm
ir intrinsic seems to have this the other way around though, and so when
lowering from one to the other we need to switch the first two outputs.

I've also fixed up the types of _pre/_post on normal MVE loads. There we
were already getting the values the right way around, just not for the
types. I don't believe this was causing anything to go wrong, but it was
very confusing to read in the debug output.

Differential Revision: https://reviews.llvm.org/D73370