[all-commits] [llvm/llvm-project] 13d4ef: Improvements to call site register worklist

[David via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 13d4ef9ac0fa02d2a8d5d01bf614b5fad852bb58
      https://github.com/llvm/llvm-project/commit/13d4ef9ac0fa02d2a8d5d01bf614b5fad852bb58
  Author: David Stenberg <david.stenberg at ericsson.com>
  Date:   2020-01-27 (Mon, 27 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    M llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
    M llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
    A llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
    A llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
    M llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir

  Log Message:
  -----------
  Improvements to call site register worklist

Summary:
This fixes PR44118. For cases where we have a chain like this:

  R8 = R1 (entry value)
  R0 = R8
  call @foo R0

the code that emits call site entries using entry values would not
follow that chain, instead emitting a call site entry with R8 as
location rather than R0. Such a case was discovered when originally
adding dbgcall-site-orr-moves.mir. This patch fixes that issue. This is
done by changing the ForwardedRegWorklist set to a map in which the
worklist registers always map to the parameter registers that they
describe.

Another thing this patch fixes is that worklist registers now can
describe more than one parameter register at a time. Such a case
occurred in dbgcall-site-interpretation.mir, resulting in a call site
entry not being emitted for one of the parameters.

Reviewers: djtodoro, NikolaPrica, aprantl, vsk

Reviewed By: vsk

Subscribers: hiraditya, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D73168