[all-commits] [llvm/llvm-project] 838a28: [RISCV] Scheduler description for the Rocket core

[Hsiangkai via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 838a28e234e098bfc073a45f37a4dd3bb5b45eab
      https://github.com/llvm/llvm-project/commit/838a28e234e098bfc073a45f37a4dd3bb5b45eab
  Author: Kai Wang <kai.wang at sifive.com>
  Date:   2020-01-23 (Thu, 23 Jan 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    A llvm/lib/Target/RISCV/RISCVSchedRocket32.td
    A llvm/lib/Target/RISCV/RISCVSchedRocket64.td
    A llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Scheduler description for the Rocket core

Pipeline scheduler model for the RISC-V Rocket micro-architecture using the
MIScheduler interface.  Support for both 32 and 64-bit Rocket cores is
implemented.

Differential revision: https://reviews.llvm.org/D68685