[all-commits] [llvm/llvm-project] 4faf71: GlobalISel: Use Register

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4faf71a14338420afc09eec261d5295439ae956a
      https://github.com/llvm/llvm-project/commit/4faf71a14338420afc09eec261d5295439ae956a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-23 (Thu, 23 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

  Log Message:
  -----------
  GlobalISel: Use Register


  Commit: 618fa77ae4dd8244e468fce0bf144fa329f41e5b
      https://github.com/llvm/llvm-project/commit/618fa77ae4dd8244e468fce0bf144fa329f41e5b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-23 (Thu, 23 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32

The other 3-op patterns should also be theoretically handled, but
currently there's a bug in the inferred pattern complexity.

I'm not sure what the error handling strategy should be for potential
constant bus violations. I think the correct strategy is to never
produce mixed SGPR and VGPR operands in a typical VOP instruction,
which will trivially avoid them. However, it's possible to still have
hand written MIR (or erroneously transformed code) with these
operands. When these fold, the restriction will be violated. We
currently don't have any verifiers for reg bank legality. For now,
just ignore the restriction.

It might be worth triggering a DAG fallback on verifier error.


Compare: https://github.com/llvm/llvm-project/compare/e256a775ebfc...618fa77ae4dd