[all-commits] [llvm/llvm-project] d1de6d: [X86][SSE] Add ComputeNumSignBits tests for (ADD (...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d1de6dc17cdd37f84e92da5a456099eab0cc1467
      https://github.com/llvm/llvm-project/commit/d1de6dc17cdd37f84e92da5a456099eab0cc1467
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-23 (Thu, 23 Jan 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/sar_fold64.ll

  Log Message:
  -----------
  [X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors


  Commit: 0fec8acdd82a69fc5419b4a9db3c92a86634729d
      https://github.com/llvm/llvm-project/commit/0fec8acdd82a69fc5419b4a9db3c92a86634729d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-23 (Thu, 23 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/sar_fold64.ll

  Log Message:
  -----------
  [SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support

Add missing handling for (ADD (AND X, 1), -1) uniform vectors


Compare: https://github.com/llvm/llvm-project/compare/59f95222d4c5...0fec8acdd82a