[all-commits] [llvm/llvm-project] f14f2a: [LV] Fix predication for branches with matching tr...

[Florian Hahn via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f14f2a856802e086662d919e2ead641718b27555
      https://github.com/llvm/llvm-project/commit/f14f2a856802e086662d919e2ead641718b27555
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2020-01-22 (Wed, 22 Jan 2020)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    A llvm/test/Transforms/LoopVectorize/pr44488-predication.ll

  Log Message:
  -----------
  [LV] Fix predication for branches with matching true and false succs.

Currently due to the edge caching, we create wrong predicates for
branches with matching true and false successors. We will cache the
condition for the edge from the true successor, and then lookup the same
edge (src and dst are the same) for the edge to the false successor.

If both successors match, the condition should always be true. At the
moment, we cannot really create constant VPValues, but we can just
create a true condition as X | !X. Later passes will clean that up.

Fixes PR44488.

Reviewers: rengolin, hsaito, fhahn, Ayal, dorit, gilr

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D73079