[all-commits] [llvm/llvm-project] d64ca7: [SLP] Add a test showing miscompilation in AltOpco...

[aelovikov-intel via All-commits]

  Branch: refs/heads/release/10.x
  Home:   https://github.com/llvm/llvm-project
  Commit: d64ca7abe191e5813ab171df325f2cc2693dae21
      https://github.com/llvm/llvm-project/commit/d64ca7abe191e5813ab171df325f2cc2693dae21
  Author: Andrei Elovikov <andrei.elovikov at intel.com>
  Date:   2020-01-23 (Thu, 23 Jan 2020)

  Changed paths:
    A llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll

  Log Message:
  -----------
  [SLP] Add a test showing miscompilation in AltOpcode support

Reviewers: Vasilis, RKSimon, ABataev

Reviewed By: RKSimon, ABataev

Subscribers: ABataev, inglorion, dexonsmith, llvm-commits, vdmitrie

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72739

(cherry picked from commit 757fe53994c1792cbdc84526696a0e256345911f)


  Commit: 029140ee1ca99e23558c774bb23257a4ea796069
      https://github.com/llvm/llvm-project/commit/029140ee1ca99e23558c774bb23257a4ea796069
  Author: Andrei Elovikov <andrei.elovikov at intel.com>
  Date:   2020-01-23 (Thu, 23 Jan 2020)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll

  Log Message:
  -----------
  [SLP] Don't allow Div/Rem as alternate opcodes

Summary:
We don't have control/verify what will be the RHS of the division, so it might
happen to be zero, causing UB.

Reviewers: Vasilis, RKSimon, ABataev

Reviewed By: ABataev

Subscribers: vporpo, ABataev, hiraditya, llvm-commits, vdmitrie

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72740

(cherry picked from commit e1d6d368529322edc658c893c01eaadaf8053ea6)


Compare: https://github.com/llvm/llvm-project/compare/1f98c2b586e4...029140ee1ca9