[all-commits] [llvm/llvm-project] 67a877: [AArch64] Don't generate gpr CSEL instructions in ...

[AE via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 67a87753225e7f5ad5b1fd151d6d2dde3d09ff09
      https://github.com/llvm/llvm-project/commit/67a87753225e7f5ad5b1fd151d6d2dde3d09ff09
  Author: Amara Emerson <aemerson at apple.com>
  Date:   2020-01-21 (Tue, 21 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.h
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.h
    A llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir

  Log Message:
  -----------
  [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible.

In GlobalISel we may in some unfortunate circumstances generate PHIs with
operands that are on separate banks. If-conversion doesn't currently check for
that case and ends up generating a CSEL on AArch64 with incorrect register
operands.

Differential Revision: https://reviews.llvm.org/D72961