[all-commits] [llvm/llvm-project] ec9628: AMDGPU/GlobalISel: Select DS append/consume

Fri Jan 17 17:09:58 PST 2020

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ec9628318d797bfe036aca314d58665dd93b364f
      https://github.com/llvm/llvm-project/commit/ec9628318d797bfe036aca314d58665dd93b364f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-17 (Fri, 17 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.append.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.consume.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Select DS append/consume

  Commit: 592de0009f6482fbf033ef87d147aab13fcce78c
      https://github.com/llvm/llvm-project/commit/592de0009f6482fbf033ef87d147aab13fcce78c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-17 (Fri, 17 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Select llvm.amdgcn.update.dpp

The existing test is overly reliant on -mattr=-flat-for-global, and
some missing optimizations to re-use.

  Commit: a4451d88ee456304c26d552749aea6a7f5154bde
      https://github.com/llvm/llvm-project/commit/a4451d88ee456304c26d552749aea6a7f5154bde
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-17 (Fri, 17 Jan 2020)

  Changed paths:
    M clang/include/clang/Basic/CodeGenOptions.def
    M clang/include/clang/Basic/CodeGenOptions.h
    M clang/include/clang/Driver/CC1Options.td
    M clang/include/clang/Driver/Options.td
    M clang/include/clang/Driver/ToolChain.h
    M clang/lib/Basic/Targets/AMDGPU.cpp
    M clang/lib/CodeGen/CGCall.cpp
    M clang/lib/CodeGen/CodeGenModule.cpp
    M clang/lib/Driver/ToolChains/AMDGPU.cpp
    M clang/lib/Driver/ToolChains/AMDGPU.h
    M clang/lib/Driver/ToolChains/Clang.cpp
    M clang/lib/Driver/ToolChains/Cuda.cpp
    M clang/lib/Driver/ToolChains/Cuda.h
    M clang/lib/Driver/ToolChains/HIP.cpp
    M clang/lib/Frontend/CompilerInvocation.cpp
    M clang/test/CodeGenCUDA/flush-denormals.cu
    M clang/test/CodeGenCUDA/propagate-metadata.cu
    M clang/test/CodeGenOpenCL/amdgpu-features.cl
    R clang/test/CodeGenOpenCL/denorms-are-zero.cl
    R clang/test/CodeGenOpenCL/gfx9-fp32-denorms.cl
    A clang/test/Driver/cl-denorms-are-zero.cl
    A clang/test/Driver/cuda-flush-denormals-to-zero.cu
    M clang/test/Driver/denormal-fp-math.c
    M clang/test/Driver/opencl.cl
    M llvm/docs/LangRef.rst
    M llvm/lib/CodeGen/MachineFunction.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    M llvm/test/CodeGen/NVPTX/fast-math.ll
    M llvm/test/CodeGen/NVPTX/math-intrins.ll
    M llvm/test/CodeGen/NVPTX/sqrt-approx.ll
    M llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll

  Log Message:
  -----------
  Consolidate internal denormal flushing controls

Currently there are 4 different mechanisms for controlling denormal
flushing behavior, and about as many equivalent frontend controls.

- AMDGPU uses the fp32-denormals and fp64-f16-denormals subtarget features
- NVPTX uses the nvptx-f32ftz attribute
- ARM directly uses the denormal-fp-math attribute
- Other targets indirectly use denormal-fp-math in one DAGCombine
- cl-denorms-are-zero has a corresponding denorms-are-zero attribute

AMDGPU wants a distinct control for f32 flushing from f16/f64, and as
far as I can tell the same is true for NVPTX (based on the attribute
name).

Work on consolidating these into the denormal-fp-math attribute, and a
new type specific denormal-fp-math-f32 variant. Only ARM seems to
support the two different flush modes, so this is overkill for the
other use cases. Ideally we would error on the unsupported
positive-zero mode on other targets from somewhere.

Move the logic for selecting the flush mode into the compiler driver,
instead of handling it in cc1. denormal-fp-math/denormal-fp-math-f32
are now both cc1 flags, but denormal-fp-math-f32 is not yet exposed as
a user flag.

-cl-denorms-are-zero, -fcuda-flush-denormals-to-zero and
-fno-cuda-flush-denormals-to-zero will be mapped to
-fp-denormal-math-f32=ieee or preserve-sign rather than the old
attributes.

Stop emitting the denorms-are-zero attribute for the OpenCL flag. It
has no in-tree users. The meaning would also be target dependent, such
as the AMDGPU choice to treat this as only meaning allow flushing of
f32 and not f16 or f64. The naming is also potentially confusing,
since DAZ in other contexts refers to instructions implicitly treating
input denormals as zero, not necessarily flushing output denormals to
zero.

This also does not attempt to change the behavior for the current
attribute. The LangRef now states that the default is ieee behavior,
but this is inaccurate for the current implementation. The clang
handling is slightly hacky to avoid touching the existing
denormal-fp-math uses. Fixing this will be left for a future patch.

AMDGPU is still using the subtarget feature to control the denormal
mode, but the new attribute are now emitted. A future change will
switch this and remove the subtarget features.

  Commit: df7900e2182467fe11637c657d7d9fa9d9b61f48
      https://github.com/llvm/llvm-project/commit/df7900e2182467fe11637c657d7d9fa9d9b61f48
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-17 (Fri, 17 Jan 2020)

  Changed paths:
    M llvm/test/TableGen/GlobalISelEmitter-input-discard.td

  Log Message:
  -----------
  TableGen/GlobalISel: Don't check exact intrinsic opcode value

Compare: https://github.com/llvm/llvm-project/compare/423e3db6a820...df7900e21824