[all-commits] [llvm/llvm-project] be31a7: GlobalISel: Move extension scalar narrowing to sep...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: be31a7b7eec8ed7c033f3087dd88e8fd685c3ded
      https://github.com/llvm/llvm-project/commit/be31a7b7eec8ed7c033f3087dd88e8fd685c3ded
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  Log Message:
  -----------
  GlobalISel: Move extension scalar narrowing to separate function

Also rename a few things. Handling a different requested type will
require this to become much more complex.


  Commit: a66d2817ca9e1dd72674627b18aec80d077910f0
      https://github.com/llvm/llvm-project/commit/a66d2817ca9e1dd72674627b18aec80d077910f0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

  Log Message:
  -----------
  GlobalISel: Don't ignore requested ext narrowing type

This was assuming the narrow target was the source type. Respect the
requested type when these don't match by using intermediate
merges. This avoids producing very wide, illegal shift expansions.


  Commit: e12b840abfcde8ec02062fa7600348ad4623d049
      https://github.com/llvm/llvm-project/commit/e12b840abfcde8ec02062fa7600348ad4623d049
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Improve lowering of G_SEXT_INREG

Clamping the scalar is much better than lowering with superwide shifts
for types > s64.


  Commit: 8945b23af590286d3a48e72d59348eb218bb7fbd
      https://github.com/llvm/llvm-project/commit/8945b23af590286d3a48e72d59348eb218bb7fbd
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
    M llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll

  Log Message:
  -----------
  AMDGPU: Update more tests to use modern buffer intrinsics


Compare: https://github.com/llvm/llvm-project/compare/5f65065437cd...8945b23af590