[all-commits] [llvm/llvm-project] fa9dd8: [mlir] Refactor ModuleState into AsmState and expo...

[River Riddle via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fa9dd8336bbd1167926f93fe2018d0c47839d5d6
      https://github.com/llvm/llvm-project/commit/fa9dd8336bbd1167926f93fe2018d0c47839d5d6
  Author: River Riddle <riverriddle at google.com>
  Date:   2020-01-14 (Tue, 14 Jan 2020)

  Changed paths:
    A mlir/include/mlir/IR/AsmState.h
    M mlir/include/mlir/IR/Block.h
    M mlir/include/mlir/IR/Module.h
    M mlir/include/mlir/IR/OpDefinition.h
    M mlir/include/mlir/IR/Operation.h
    M mlir/include/mlir/IR/Value.h
    M mlir/lib/IR/AsmPrinter.cpp

  Log Message:
  -----------
  [mlir] Refactor ModuleState into AsmState and expose it to users.

Summary:
This allows for users to cache printer state, which can be costly to recompute. Each of the IR print methods gain a new overload taking this new state class.

Depends On D72293

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D72294