[all-commits] [llvm/llvm-project] c6fcd5: [SelectionDAG] ComputeNumSignBits add getValidMaxi...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c6fcd5d115b62280669719c5ead436904c93d6cb
      https://github.com/llvm/llvm-project/commit/c6fcd5d115b62280669719c5ead436904c93d6cb
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-13 (Mon, 13 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/known-signbits-vector.ll

  Log Message:
  -----------
  [SelectionDAG] ComputeNumSignBits add getValidMaximumShiftAmountConstant() for ISD::SHL support

Allows us to handle non-uniform SHL shifts to determine the minimum number of sign bits remaining (based off the maximum shift amount value)