[all-commits] [llvm/llvm-project] ee4aa1: [X86] Add AVX2 known signbits codegen tests

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ee4aa1a228b31ec8b8bd3c4a793c7fa92fec88d6
      https://github.com/llvm/llvm-project/commit/ee4aa1a228b31ec8b8bd3c4a793c7fa92fec88d6
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-13 (Mon, 13 Jan 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/known-signbits-vector.ll

  Log Message:
  -----------
  [X86] Add AVX2 known signbits codegen tests


  Commit: 7afaa0099b907842b281c25c2a57937a2c307d3b
      https://github.com/llvm/llvm-project/commit/7afaa0099b907842b281c25c2a57937a2c307d3b
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-13 (Mon, 13 Jan 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/known-signbits-vector.ll

  Log Message:
  -----------
  [X86][SSE] Add sitofp(ashr(x,y)) test case with non-uniform shift value


  Commit: 38e2c01221a9751c0b797417747200d2e9513b9f
      https://github.com/llvm/llvm-project/commit/38e2c01221a9751c0b797417747200d2e9513b9f
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-13 (Mon, 13 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/known-signbits-vector.ll

  Log Message:
  -----------
  [SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() ISD::SRA support

Allows us to handle more non-uniform SRA sign bits cases


Compare: https://github.com/llvm/llvm-project/compare/90555d925343...38e2c01221a9