[all-commits] [llvm/llvm-project] 0113cf: [RISCV] Check register class for AMO memory operands

[James Clarke via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0113cf193f0610bb1a5dfa0bcd29c41a8965938a
      https://github.com/llvm/llvm-project/commit/0113cf193f0610bb1a5dfa0bcd29c41a8965938a
  Author: James Clarke <jrtc27 at jrtc27.com>
  Date:   2020-01-13 (Mon, 13 Jan 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/test/MC/RISCV/rva-aliases-invalid.s

  Log Message:
  -----------
  [RISCV] Check register class for AMO memory operands

Summary:
AMO memory operands use a custom parser in order to accept both (reg)
and 0(reg). However, the validation predicate used for these operands
was only checking that they were registers, and not the register class,
so non-GPRs (such as FPRs) were also accepted. Thus, fix this by making
the predicate check that they are GPRs.

Reviewers: asb, lenary

Reviewed By: asb, lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72471