[all-commits] [llvm/llvm-project] 255cc5: CodeGen: Use LLT instead of EVT in getRegisterByName

Thu Jan 9 14:38:21 PST 2020

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 255cc5a7603fef251192daab2a3336acbcd9aa1c
      https://github.com/llvm/llvm-project/commit/255cc5a7603fef251192daab2a3336acbcd9aa1c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-09 (Thu, 09 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLowering.h
    M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
    M llvm/lib/Target/Lanai/LanaiISelLowering.h
    M llvm/lib/Target/Mips/MipsISelLowering.cpp
    M llvm/lib/Target/Mips/MipsISelLowering.h
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/Sparc/SparcISelLowering.cpp
    M llvm/lib/Target/Sparc/SparcISelLowering.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h

  Log Message:
  -----------
  CodeGen: Use LLT instead of EVT in getRegisterByName

Only PPC seems to be using it, and only checks some simple cases and
doesn't distinguish between FP. Just switch to using LLT to simplify
use from GlobalISel.

  Commit: ac53a5f1dc21916f1072031703e0e1833e963454
      https://github.com/llvm/llvm-project/commit/ac53a5f1dc21916f1072031703e0e1833e963454
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-09 (Thu, 09 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/LowLevelType.cpp

  Log Message:
  -----------
  GlobalISel: Fix else after return

  Commit: f33f3d98e9e6322846c3b997260faf3e1165e0dd
      https://github.com/llvm/llvm-project/commit/f33f3d98e9e6322846c3b997260faf3e1165e0dd
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-09 (Thu, 09 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

  Log Message:
  -----------
  DAG: Don't use unchecked dyn_cast

  Commit: 0ea3c7291fb8d463d9c7ae6aaec7a432ef366a51
      https://github.com/llvm/llvm-project/commit/0ea3c7291fb8d463d9c7ae6aaec7a432ef366a51
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-09 (Thu, 09 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/read_register.ll

  Log Message:
  -----------
  GlobalISel: Handle llvm.read_register

Compared to the attempt in bdcc6d3d2638b3a2c99ab3b9bfaa9c02e584993a,
this uses intermediate generic instructions.

  Commit: b4a647449fa01bd4e29bce5afef51770cddec664
      https://github.com/llvm/llvm-project/commit/b4a647449fa01bd4e29bce5afef51770cddec664
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-09 (Thu, 09 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    M llvm/include/llvm/Target/GlobalISel/Target.td
    M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
    A llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
    M llvm/test/TableGen/GlobalISelEmitter.td
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  TableGen/GlobalISel: Add way for SDNodeXForm to work on timm

The current implementation assumes there is an instruction associated
with the transform, but this is not the case for
timm/TargetConstant/immarg values. These transforms should directly
operate on a specific MachineOperand in the source
instruction. TableGen would assert if you attempted to define an
equivalent GISDNodeXFormEquiv using timm when it failed to find the
instruction matcher.

Specially recognize SDNodeXForms on timm, and pass the operand index
to the render function.

Ideally this would be a separate render function type that looks like
void renderFoo(MachineInstrBuilder, const MachineOperand&), but this
proved to be somewhat mechanically painful. Add an optional operand
index which will only be passed if the transform should only look at
the one source operand.

Theoretically it would also be possible to only ever pass the
MachineOperand, and the existing renderers would check the parent. I
think that would be somewhat ugly for the standard usage which may
want to inspect other operands, and I also think MachineOperand should
eventually not carry a pointer to the parent instruction.

Use it in one sample pattern. This isn't a great example, since the
transform exists to satisfy DAG type constraints. This could also be
avoided by just changing the MachineInstr's arbitrary choice of
operand type from i16 to i32. Other patterns have nontrivial uses, but
this serves as the simplest example.

One flaw this still has is if you try to use an SDNodeXForm defined
for imm, but the source pattern uses timm, you still see the "Failed
to lookup instruction" assert. However, there is now a way to avoid
it.

  Commit: 10edb1d0d4a15812a71f8953bba96a4f1fc9d0af
      https://github.com/llvm/llvm-project/commit/10edb1d0d4a15812a71f8953bba96a4f1fc9d0af
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-09 (Thu, 09 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    M llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
    A llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
    M llvm/utils/TableGen/CodeGenInstruction.cpp
    M llvm/utils/TableGen/CodeGenInstruction.h
    M llvm/utils/TableGen/CodeGenIntrinsics.h
    M llvm/utils/TableGen/CodeGenTarget.cpp
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  TableGen/GlobalISel: Fix pattern matching of immarg literals

For arguments that are not expected to be materialized with
G_CONSTANT, this was emitting predicates which could never match. It
was first adding a meaningless LLT check, which would always fail due
to the operand not being a register.

Infer the cases where a literal should check for an immediate operand,
instead of a register This avoids needing to invent a special way of
representing timm literal values.

Also handle immediate arguments in GIM_CheckLiteralInt. The comments
stated it handled isImm() and isCImm(), but that wasn't really true.

This unblocks work on the selection of all of the complicated AMDGPU
intrinsics in future commits.

Compare: https://github.com/llvm/llvm-project/compare/cc95bb1f57c6...10edb1d0d4a1