[all-commits] [llvm/llvm-project] b93766: [X86] Improve lowering of v2i64 sign bit tests on ...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b9376690a011765e35d9ca63abe0e7117985f1ed
      https://github.com/llvm/llvm-project/commit/b9376690a011765e35d9ca63abe0e7117985f1ed
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/bitcast-vector-bool.ll
    M llvm/test/CodeGen/X86/movmsk-cmp.ll
    M llvm/test/CodeGen/X86/sadd_sat_vec.ll
    M llvm/test/CodeGen/X86/ssub_sat_vec.ll
    M llvm/test/CodeGen/X86/vec_saddo.ll

  Log Message:
  -----------
  [X86] Improve lowering of v2i64 sign bit tests on pre-sse4.2 targets

Without sse4.2 a v2i64 setlt needs to expand into a pcmpgtd, pcmpeqd, 3 shuffles, and 2 logic ops. But if we're only interested in the sign bit of the i64 elements, we can just use one pcmpgtd and shuffle the odd elements to the even elements.

Differential Revision: https://reviews.llvm.org/D72302


  Commit: afa8211e979c25100c2ed41d8da1e18b45d0ef2b
      https://github.com/llvm/llvm-project/commit/afa8211e979c25100c2ed41d8da1e18b45d0ef2b
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-pcmp.ll

  Log Message:
  -----------
  [X86] Improve lowering of (v2i64 (setgt X, -1)) on pre-SSE2 targets. Enable v2i64 in foldVectorXorShiftIntoCmp.

Similar to D72302 but for the canonical form for the opposite case. I've changed foldVectorXorShiftIntoCmp to form a target independent setcc node instead of PCMPGT now and enabled its for v2i64 on pre-SSE4.2 targets. The setcc should eventually get lowered to PCMPGT or the new v2i64 sequence.

Differential Revision: https://reviews.llvm.org/D72318


Compare: https://github.com/llvm/llvm-project/compare/2f1e5d934e24...afa8211e979c