[all-commits] [llvm/llvm-project] 58e2e9: [DAGCombiner] reduce shuffle of concat of same vector

[RotateRight via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 58e2e92a57fcc3c628fd03ae33698fcc9aabedb9
      https://github.com/llvm/llvm-project/commit/58e2e92a57fcc3c628fd03ae33698fcc9aabedb9
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll

  Log Message:
  -----------
  [DAGCombiner] reduce shuffle of concat of same vector

This is possibly a small part towards solving PR42024:
https://bugs.llvm.org/show_bug.cgi?id=42024

The vectorizer is creating shuffles of concat like this:

%63 = shufflevector <4 x i64> %x, <4 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%64 = shufflevector <8 x i64> %63, <8 x i64> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>

That might be fixable in the vectorizers, but we're not allowed to fold that into a single shuffle in instcombine,
so we should have a backend backstop to convert that into the likely simpler form:

%64 = shufflevector <4 x i64> %x, <4 x i64> undef, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>

Differential Revision: https://reviews.llvm.org/D72300